SoC stands for System on Chip. Many electronic applications are based on microprocessors, memories, and peripherals. Traditionally the integration of these system components has been done at the board (PCB) level.
The never-stopping progression in electronic miniaturization has made it possible for many of these components (processor, memories, peripherals) to be integrated into a single package, thus called SoC.
Continue reading “SoC and MPSoC, what you wanted to know”
Continue reading “Free Range VHDL – free book”The purpose of this book is to provide students and young engineers with a guide to help them develop the skills necessary to be able to use VHDL for introductory and intermediate level digital design
The Basys 3 board has a plethora of interactive resources: push buttons, switches, LEDs, and a four-digit seven-segment display, among others.
In this series of articles, we will describe Magellan. Magellan is a hardware monitor/debugger which we will put to use for debugging our designs.
Continue reading “Magellan – a hardware monitor/debugger”
Image credit: Digilent
This project is a very basic and simple project. Four of the board LEDs are blinked using a counter. The position of switch 0 makes the blinking faster or slower.
For an introduction to the Basys3 board, check here.
Continue reading “Basys 3 basic LED flasher”Free Range’s author James Mealy has a long trajectory in the free diffusion of logic design.
On this site, you can find free books (Logic foundation and Verilog), selected chapters of the course on video, and solutions to the course’s lab exercises.
From the author page :
I started collecting digital design textbooks after arriving at Cal Poly; I was sure that writing books meant having all the books possible on the subject and arranging the information differently. What I found was that I simply didn’t like the approach taken in every digital design textbook I’ve ever read. This led me to take a different approach, which I’ve done in the FreeRange series of courseware. I put more comments regarding the approach on a different page and in the actual textbooks as well.
Free Range – Digital Design and Verilog Modeling
You may also want to check: Free Range VHDL (free book)
Basys 3 board with several PMOD boards attached – Credit: Digilent
The Basys 3 from Digilent is an FPGA Trainer Board based on AMD Xilinx’s Artix-7 FPGA.
In future blog entries, I will be including several projects based on this Trainer Board.
Continue reading “Basys 3 – An introduction”The motto of this blog is “FPGA projects in VHDL”. It also includes free VHDL books. But, in a past comment on Hacker News, I saw this nice Verilog short guide and I knew I have to share it here.
Continue reading “Introduction to Verilog”A modulo counter is a counter that wraps around when it reaches a certain value. For example, a counter modulo 5 will count 0, 1, 2, 3, 4, 0, 1, …; namely, after 4 it will wrap around to 0. The reason the counter wraps after 4 is that to count five clock pulses starting from zero, the maximum value of the counter must be (modulo-1), in this case, 5-1=4.
Every VHDL counter is a modulo counter. If you define a two-bit counter, it will wrap around automatically from 3 to 0 without the need of writing special logic for that.
Continue reading “VHDL Modulo counter, how to code and test it”by Gilad Krupsky Reisman
The AXI Chip2Chip IP from Xilinx allows the designer to connect two or more FPGAs using an AXI bus implemented using transceivers running the Aurora64/66 protocol. While there is also an option to use regular FPGA pins if you don’t have transceivers, in my experience, it takes up too many pins to be relevant.
Continue reading “Xilinx AXI Chip2Chip for multi-FPGA design”For me, and for many other designers, the first time we saw the internal memory blocks in an FPGA came as a little shock.
Some of us were used to RAM devices used in Board Design. These devices use bidirectional data buses. Even the fastest memories, DDRn DRAMs, use bidirectional data buses (‘n’ has changed over the years, from plain DDR to current DDR4).
So, how come internal memories on an FPGA have TWO data buses? Isn’t that a waste of resources? Why don’t FPGAs have internal tri-state buses?
Continue reading “FPGA internal tri-state buses”