by Gilad Krupsky Reisman

The AXI Chip2Chip IP from Xilinx allows the designer to connect two or more FPGAs using an AXI bus implemented using transceivers running the Aurora64/66 protocol. While there is also an option to use regular FPGA pins if you don’t have transceivers, in my experience, it takes up too many pins to be relevant.

Continue reading “Xilinx AXI Chip2Chip for multi-FPGA design” →