Continue reading “Parallel Programming for FPGAs”Parallel Programming for FPGAs is an open-source book aimed at teaching hardware and software developers how to efficiently program FPGAs using high-level synthesis (HLS). The authors developed the book as we noticed a lack of material aimed at teaching people to effectively use HLS tools.
The book was developed over many years to serve as a primary reference for UCSD 237C — a hardware design class targeting first-year graduate students and advanced undergraduate students. We hope that you find it useful for learning more about HLS, FPGAs, and system-on-chip design.
Tag: HLS
A Fresh Look at HLS Value
by Bernard Murphy
I’ve written several articles on High-Level Synthesis (HLS), designing in C, C++, or SystemC, then synthesizing to RTL. There is an unquestionable appeal to the concept. A higher level of abstraction enables a function to be described in fewer lines of code (LOC). This immediately offers higher productivity and implies fewer bugs because the number of bugs in any kind of code scales pretty reliably with LOC. Simulation for architectural design and validation runs multiple orders of magnitude faster, allowing for broader experimentation with options. It also can run much larger tests like image recognition on streaming video, a tough goal for RTL simulations. Yet these methods have largely been restricted to specialized design objectives it seemed. Signal processing functions, some simple ML inference engines, that sort of thing.
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