An Entity defines the interface of a design unit. The elements of an entity are:
- Name of the entity
- Generic parameters
- Ports (connections of the entity)
- The most popular port types are in, out, and inout.
The architecture specifies the behavior of an entity. An entity can be bonded to several architectures. Each architecture sees all the elements (ports, parameters) of the entity.
A component consists of an entity and architecture pair. A component must first be declared. The declaration is a ‘virtual’ action, a declared component is doing nothing until it is instantiated.
The instantiation of a component is compared, many times, to the act of connecting a physical chip to its socket. A component can be instantiated multiple times in a design.
A component can be instantiated without a component declaration. Many designers prefer this approach, which was introduced on VHDL ’93 (direct instantiation). Direct instantiation eliminates the need to update added or changed parameters and ports in two different places (component declaration and component instantiation).
Some VHDL entry tools (like HDL designer) manage component declaration and instantiation automatically based on a graphic representation of the design.