Hi again,

In the previous chapter of this tutorial, we presented the AXI Streaming interface, its main signals, and some of its applications.

Now let’s go for the funnier stuff, that is, to actually make and test some VHDL code to implement our AXI master. We will proceed gradually, adding features as we go. At the end of this tutorial, you will have code that:

• Implements an AXI master with variable packet length
• Flow control support (ready and valid)
• Option for generation of several kinds of data patterns
• Testbench to check that all features work OK
• Include an instantiation of Xilinx’s AXI Stream protocol checker IP to verify the correctness of our AXI master core.

Continue reading “Xilinx AXI stream tutorial – Part 2” →

Hi,

In this series of articles, I am going to present the design of an AXI4-Stream master. As I often do in my tutorials, I will try to show the design procedure for the block, starting from a “bare bones” solution and gradually adding features to it.

Continue reading “Xilinx AXI Stream Tutorial” →