AMD-Xilinx extends series-7 product lifecycle

The 28nm AMD-Xilinx 7 series devices are used in industrial, automotive, test and measurement, aerospace and defense, and medical markets.

AMD-Xilinx has formally announced extended support for all 7 series FPGAs and adaptive SoCs through at least 2035, including the Spartan®-7 and Artix®-7 FPGAs, the entire Zynq®-7000 SoC portfolio, as well as Kintex®-7 and Virtex®-7 FPGAs. All speed and temperature grades are included.

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Sphery vs. Shapes, a ray-traced game implemented on FPGA

As published on Reddit:

An open-source raytraced game runs as software or as just gates in an FPGA, achieving up to 50x efficiency gains.

The project was featured in the embedded news site CNX-Software today. An introductory video is at https://www.youtube.com/watch?v=hn3sr3VMJQU.

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SoC and MPSoC, what you wanted to know

Image credit: Xilinx

SoC stands for System on Chip. Many electronic applications are based on microprocessors, memories, and peripherals. Traditionally the integration of these system components has been done at the board (PCB) level.

The never-stopping progression in electronic miniaturization has made it possible for many of these components (processor, memories, peripherals) to be integrated into a single package, thus called SoC.

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Xilinx AXI Chip2Chip for multi-FPGA design

by Gilad Krupsky Reisman

The AXI Chip2Chip IP from Xilinx allows the designer to connect two or more FPGAs using an AXI bus implemented using transceivers running the Aurora64/66 protocol. While there is also an option to use regular FPGA pins if you don’t have transceivers, in my experience, it takes up too many pins to be relevant.

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FPGA internal tri-state buses

For me, and for many other designers, the first time we saw the internal memory blocks in an FPGA came as a little shock.

Some of us were used to RAM devices used in Board Design. These devices use bidirectional data buses. Even the fastest memories, DDRn DRAMs, use bidirectional data buses (‘n’ has changed over the years, from plain DDR to current DDR4).

So, how come internal memories on an FPGA have TWO data buses? Isn’t that a waste of resources? Why don’t FPGAs have internal tri-state buses?

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