Category: Technical Articles

Intel announces new FPGA families

Image source: Intel PSG

Intel has announced these new/future FPGA families:

Intel® Agilex™ D-Series

For midrange FPGA applications like studio cameras, 8K video transport, and wireless infrastructure.

This new family incorporates an upgraded hard processor system (HPS), Enhanced DSP with AI Tensor Block, MIPI I/O support, and a hardened time-sensitive network controller (TSN). Intel Agilex D-Series devices also keep features from previous families like the 2nd-generation Intel® Hyperflex™ FPGA Architecture and high-speed SerDes transceivers.

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Xilinx AXI stream tutorial – Part 2

Hi again,

In the previous chapter of this tutorial, we presented the AXI Streaming interface, its main signals, and some of its applications.

Now let’s go for the funnier stuff, that is, to actually make and test some VHDL code to implement our AXI master. We will proceed gradually, adding features as we go. At the end of this tutorial, you will have code that:

  • Implements an AXI master with variable packet length
  • Flow control support (ready and valid)
  • Option for generation of several kinds of data patterns
  • Testbench to check that all features work OK
  • Include an instantiation of Xilinx’s AXI Stream protocol checker IP to verify the correctness of our AXI master core.
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SoC and MPSoC, what you wanted to know

Image credit: Xilinx

SoC stands for System on Chip. Many electronic applications are based on microprocessors, memories, and peripherals. Traditionally the integration of these system components has been done at the board (PCB) level.

The never-stopping progression in electronic miniaturization has made it possible for many of these components (processor, memories, peripherals) to be integrated into a single package, thus called SoC.

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Xilinx AXI Chip2Chip for multi-FPGA design

by Gilad Krupsky Reisman

The AXI Chip2Chip IP from Xilinx allows the designer to connect two or more FPGAs using an AXI bus implemented using transceivers running the Aurora64/66 protocol. While there is also an option to use regular FPGA pins if you don’t have transceivers, in my experience, it takes up too many pins to be relevant.

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Coverage analysis in Questa Visualizer

by Bernard Murphy

Coverage analysis is how you answer the question “have I tested enough?” You need some way to quantify the completeness of our testing; coverage is how you do that. Right out of the gate this is a bit deceptive. To truly cover a design our tests would need to cover every accessible state and state transition. The complexity of that task routinely invokes comparisons with the number of protons in the universe so instead, you use proxies for coverage. Touching every line in the RTL, exercising every branch, every function, every assertion, and so on. Each is a far cry from exhaustive coverage., but as heuristics, they work surprisingly well.

Check the rest of this article at SemiWiki


A Fresh Look at HLS Value

by Bernard Murphy

I’ve written several articles on High-Level Synthesis (HLS), designing in C, C++, or SystemC, then synthesizing to RTL. There is an unquestionable appeal to the concept. A higher level of abstraction enables a function to be described in fewer lines of code (LOC). This immediately offers higher productivity and implies fewer bugs because the number of bugs in any kind of code scales pretty reliably with LOC. Simulation for architectural design and validation runs multiple orders of magnitude faster, allowing for broader experimentation with options. It also can run much larger tests like image recognition on streaming video, a tough goal for RTL simulations. Yet these methods have largely been restricted to specialized design objectives it seemed. Signal processing functions, some simple ML inference engines, that sort of thing.

To read the rest of the article, please go to SemiWiki