Category: VHDL projects

VHDL arbiters part IV – advanced simulation

Chapter 3 of this tutorial series on VHDL arbiters ended with the simulation of a round-robin arbiter. Here is the picture again, for reference:

Let’s take a look again at the marker placed at 670 ns. Two masters (1 and 2) are requesting the bus, but as we know, only one of them can receive it at a given moment, and in this case, it is master 2. But here happens something strange: Master 1 drops its request, even given the fact that it never received a grant signal! Although such behavior is possible, it is not common. The usual behavior of a master is to keep the request signal asserted until it receives a grant.

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VHDL arbiter – part III

This is the third part of a series of articles on VHDL arbiters.

In the first part, we talked about what a VHDL arbiter is.

In the second part, we saw the VHDL code for a fixed-priority VHDL arbiter.

When I talked about what a VHDL arbiter is, I gave the example of the single car we had at home, and how I had to decide who gets to use the car next Friday evening. In a typical situation, if both children ask for the car, the first thing they will account for is, who got the car the last time.

The fixed priority arbiter is the equivalent of always giving your car to the same child. It will, no doubts, create problems. If you don’t want to create problems, you will make a balanced assignment of the valued resource between the solicitors.

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VHDL arbiter – part II

In the first article of this series, we defined what an HW arbiter is.
In this entry of the tutorial, we will see a simple implementation of a VHDL arbiter.

The arbiter of this example has three request inputs and three grant outputs. It has a fixed priority for the masters. The lower the master number, the higher its priority.
The block also has a busy signal. Arbitration of the bus is done only while it is inactive. If the bus has already been granted to an agent, even if a bigger priority master requests the bus, the current transaction must complete before the arbiter grants the bus to another master.

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VHDL arbiter

What is an arbiter?

An arbiter is a very common block used on HW designs.

I think I can find the best example of an arbiter at home. When my two kids were teenagers, I had only one car. On Friday and Saturday evenings, there was usually a conflict over who got to use the car. Usually, it was on me to decide (arbiter) who got the car. Not an easy task. (I still have only one car. It just happens that my kids are not teenagers anymore, and praise the Lord, they have their own cars).

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Magellan – a hardware monitor/debugger (II)

Part 2 – Registers monitoring

In this part we will integrate several blocks:

  1. AXI infrastructure, defined on a Vivado block design, including a JTAG to AXI master
  2. AXI-Lite registers block, with adaptations for this tutorial from the original one published on Code Snippets Seven segment driver for Basys 3 (presented in part 1 of this tutorial)
  3. Seven segment decoder for Basys 3 (presented in part 1 of this tutorial)
  4. An extension of the top block that was used in part 1, to instantiate the new blocks and add additional functionality.
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Magellan – a hardware monitor/debugger

Part 1 – Seven segment display

The Basys 3 board has a plethora of interactive resources: push buttons, switches, LEDs, and a four-digit seven-segment display, among others.

In this series of articles, we will describe Magellan. Magellan is a hardware monitor/debugger which we will put to use for debugging our designs.

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Pseudo random generator – Part II

Chapter 3 – Saving the output data

In the previous chapters of this tutorial, we saw how to make a simple LFSR module in VHDL and a testbench to verify its output results.

In this chapter, we will update our test bench to add data-saving capabilities. In this way we can:

  • Compare the VHDL data output with data generated by our reference design (in our case, a Python script algorithm)
  • Analyze the data output with other tools (again, in our case, we will use Python to produce an FFT analysis of the block output).

At the end of the chapter, you will be able to find a link to a GitHub repository with the complete files.

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Pseudo random generation Tutorial

In this tutorial, we will design a VHDL block. We will start with a very simple version of the block and gradually add features to it. We will also simulate it and test its outputs using a testbench and Python. During the process we will see:

  • How to start with a simple block and gradually add features and improvements
  • How to add a test bench (simulation)
  • Saving the block data output to files (from simulation)
  • Exporting files to Python in order to:
    • Verify the results, and
    • Analyze the results (in this case, using FFT)
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