Tag: AXI

Magellan – a hardware monitor/debugger (II)

Part 2 – Registers monitoring

In this part we will integrate several blocks:

  1. AXI infrastructure, defined on a Vivado block design, including a JTAG to AXI master
  2. AXI-Lite registers block, with adaptations for this tutorial from the original one published on Code Snippets Seven segment driver for Basys 3 (presented in part 1 of this tutorial)
  3. Seven segment decoder for Basys 3 (presented in part 1 of this tutorial)
  4. An extension of the top block that was used in part 1, to instantiate the new blocks and add additional functionality.
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Xilinx AXI Chip2Chip for multi-FPGA design

by Gilad Krupsky Reisman

The AXI Chip2Chip IP from Xilinx allows the designer to connect two or more FPGAs using an AXI bus implemented using transceivers running the Aurora64/66 protocol. While there is also an option to use regular FPGA pins if you don’t have transceivers, in my experience, it takes up too many pins to be relevant.

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