Machine learning is one of the fastest growing areas of computer science, with far-reaching applications. The aim of the textbook is to introduce machine learning, and the algorithmic paradigms it offers, in a principled way.
The book, “Understanding Machine Learning: From Theory to Algorithms”, provides a theoretical account of the fundamentals underlying machine learning and the mathematical derivations that transform these principles into practical algorithms. Following a presentation of the basics, the book covers a wide array of central topics unaddressed by previous textbooks. These include a discussion of the computational complexity of learning and the concepts of convexity and stability; important algorithmic paradigms including stochastic gradient descent, neural networks, and structured output learning; and emerging theoretical concepts such as the PAC-Bayes approach and compression-based bounds.
This book was published by Xilinx in 2005. While in our very dynamic profession, some of the technologies explained can be a bit outdated, the basic concepts are there for anyone who wishes to learn or refresh his/her concepts about high-speed serial links.
In this tutorial, we will design a VHDL block. We will start with a very simple version of the block and gradually add features to it. We will also simulate it and test its outputs using a testbench and Python. During the process we will see:
How to start with a simple block and gradually add features and improvements
How to add a test bench (simulation)
Saving the block data output to files (from simulation)
The Zynq Book is dedicated to the Xilinx Zynq-7000 System on Chip (SoC) from Xilinx.
The Zynq Book is the first book about Zynq to be written in the English language. It has been produced by a team of authors from the University of Strathclyde, Glasgow, UK, with the support of Xilinx. The book is intended for people just starting out with Zynq, and engineers already working with Zynq.
f you are completely new to FPGAs, or if you want a refreshingly high-level view of what FPGAs are and what are the future trends in the field, you can download this free book from the Intel PSG site:
Coverage analysis is how you answer the question “have I tested enough?” You need some way to quantify the completeness of our testing; coverage is how you do that. Right out of the gate this is a bit deceptive. To truly cover a design our tests would need to cover every accessible state and state transition. The complexity of that task routinely invokes comparisons with the number of protons in the universe so instead, you use proxies for coverage. Touching every line in the RTL, exercising every branch, every function, every assertion, and so on. Each is a far cry from exhaustive coverage., but as heuristics, they work surprisingly well.
This question gets asked again and again, by beginners and experienced designers alike.
When I saw it posted on the FPGA group on Reddit, I liked the answer from user fft32, so with his permission, I reproduce it here with some minor changes and additions.
VHDL compared to Verilog
VHDL:
A bit verbose, clunky syntax. I never liked that different constructs have different rules for the “end” tag, like “end synth” for architectures, versus “end component mux” for components. I always find myself looking up the syntax of packages and functions.
Strongly typed: It’s a bit of a pain to have to make a (0 downto 0) vector to do something like a carry-in, but at the end of the day, it can save you time debugging problems. You don’t scratch your head as to why your 10-bit vector is only 0 to 1, because you assigned a 1-bit value to it (a thing you could do in Verilog, but in VHDL would produce a compile error). By default, in Verilog, undeclared signals default to 1-bit nets. Once I accidentally did this with a clock and it took me a while to figure out why nothing worked.
Libraries: This is good and bad for me. It’s great to wrap your code in an organized and reusable manner. However, many “everyday” functions come from libraries rather than built into the language. There are non-standard libraries like std_logic_unsigned/std_logic_signed that are used in a lot of legacy code and old code examples. They’ve since been replaced by numeric_std. The conversion between types needs functions whose format is quite annoying.
Verilog:
Writing code seems more streamlined. No component declarations, loose data types (everything is just bits, really).
C-like syntax.
The resulting code is more compact.
Low-level descriptions are closer to actual hardware.
Verilog has a poor design of its concurrency resolution scheme. Being an HDL, concurrency is obviously a very important aspect. Here is a write-up concerning this point.
At the end of the day, the two languages are really able to achieve the same designs. I think it’s good to understand code in both languages, but since mixed language support is common, I don’t see an issue sticking with the one that you prefer.
To the comments from fft32, I would add that in my opinion, Verilog with its plain syntax is easier to learn and grasp for the beginner.
Also, from my experience, Verilog tends to be dominant in the ASIC arena, while VHDL is the language of choice for most FPGA designs.
And the winner is?
Well, none of the two, at least as these words are written. In the long run, as you advance in your HDL designer career, you will be probably using both, although also probably using one of them most of the time.
If you are wondering which one you should start with, take the one that you feel more comfortable with. Or, ask colleagues and teachers which one is most needed in the market niche you want to be part of. The important thing is to grasp the structures behind the language, and not the language itself.
To be honest, it seems that both fft32 and I mostly used VHDL, so this comparison could be a little biased. But, after all, both languages are Hardware Description Languages. So what really matters are the flip-flops and gates that give life to your design, and not so much how in what language you describe them.
Whatever you choose, good luck!
Addendum
On May 2017 I put a link about this blog topic on Hacker News. For some reason, the link got a lot of hits and there also was a lively interchange of comments regarding Verilog, VHDL… and the future of HDL languages.
I have summarized some of the comments below:
It seems that Verilog got its syntax from C, and VHDL from Ada. I don’t know Ada so I couldn’t tell, but Verilog looks C’ish to me also.
System Verilog is also a language worth checking since it has powerful verification constructs.
Many people talked about what seems to be the next step, which could leave VHDL and Verilog behind (as C left Assembler behind, might I add). The next step may well be High-Level Synthesis.
Another HDL tool worth checking: MyHDL which reportedly uses the flexibility of Python for HDL editing
And last, for the lighter side of the issue, some time ago there was a competition between VHDL and Verilog… For more details, check here (actually this is very old, and I don’t think its results are conclusive, but I thought it would be fun to mention it).
If you want to check all the comments on Hacker News by yourself, here they are.
An Entity defines the interface of a design unit. The elements of an entity are:
Name of the entity
Generic parameters
Ports (connections of the entity)
The most popular port types are in, out, and inout.
The architecture specifies the behavior of an entity. An entity can be bonded to several architectures. Each architecture sees all the elements (ports, parameters) of the entity.
A component consists of an entity and architecture pair. A component must first be declared. The declaration is a ‘virtual’ action, a declared component is doing nothing until it is instantiated.
VHDL is a strongly typed language. It is also a language with quite a long history. These two facts together make the handling of signed and unsigned numbers quite confusing. Even today I see lots of code examples with bad treatment of signed and unsigned arithmetic.
Part of the history of the VHDL language is the std_logic_arithlibrary. This library is a non-standard library, or maybe I should say a de-facto standard library, created by Synopsis. I recommend not to use it, since there is an IEEE library for arithmetic operations today, ieee.numeric_std.
-- Definition of unsigned, signed, integer and std_logic_vector signals
signal u_reg : unsigned (15 downto 0);
signal s_value : signed (15 downto 0);
signal int_var : integer range 0 to 2**15-1;
signal slv : std_logic_vector(15 downto 0);
begin
-- Conversion functions / typecasting
-- unsigned/signed to std_logic_vector
slv <= std_logic_vector(u_reg);
slv <= std_logic_vector(s_value);
-- std_logic_vector to unsigned/signed
u_reg <= unsigned(slv);
s_value <= signed(slv);
-- unsigned/signed to integer
int_var <= to_integer(u_reg);
int_var <= to_integer(s_value);
-- integer to signed/unsigned
u_reg <= to_unsigned(int_var, u_reg'length);
s_value <= to_signed(int_var, s_value'length);
-- std_logic_vector to integer
int_var <= to_integer(unsigned(slv)); -- std_logic_vector is unsigned
int_var <= to_integer(signed(slv)); -- std_logic_vector is signed
-- integer to std_logic_vector
slv <= std_logic_vector(to_unsigned(int_var, slv'length)); -- std_logic_vector is unsigned
slv <= std_logic_vector(to_signed(int_var, slv'length)); -- std_logic_vector is signed
Adding to the confusion is the fact of how operations are made for binary coded numbers. Unsigned numbers represent natural numbers from zero to the maximum value that can be coded in the vector. If we use 8-bit vectors, we will be able to code values between 0-255. To represent signed numbers, one popular format is two’s complement. Using the two’s-complement format we can code numbers from -128 to 127 in an eight-bit vector.
Unless told beforehand, VHDL has to know if a number is signed or unsigned. I will give you what I think are MUSTs and also some recommendations to work with numbers and avoid pitfalls.
Use ieee.numeric_std. DO NOT use std_logic_arith.
Be very careful when using the signed or unsigned libraries. When you use these libraries, all the std_logic_vector arrays in the file are considered signed or unsigned by default. This can cause very difficult to track bugs if there are mixed types (signed/unsigned) on the same VHDL file.
Signals that should be treated as signed or unsigned are EXPLICITLY declared as such in your source file.
