Prototypical – FPGA prototyping free book

Making FPGA prototyping part of the design process early means actually thinking about how the design will be prototyped via an FPGA

In Prototypical – The Emergence of FPGA prototyping for SoC Design book, the authors tell the history of FPGA-based prototyping and three leading system providers – S2C, Cadence, and Synopsys.

First, the book describes how the need for co-verification evolved with chip complexity, where FPGAs got their start in verification, and why ASIC design benefits from prototyping technology.

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Intel announces new FPGA families

Image source: Intel PSG

Intel has announced these new/future FPGA families:

Intel® Agilex™ D-Series

For midrange FPGA applications like studio cameras, 8K video transport, and wireless infrastructure.

This new family incorporates an upgraded hard processor system (HPS), Enhanced DSP with AI Tensor Block, MIPI I/O support, and a hardened time-sensitive network controller (TSN). Intel Agilex D-Series devices also keep features from previous families like the 2nd-generation Intel® Hyperflex™ FPGA Architecture and high-speed SerDes transceivers.

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VHDL arbiter – part II

In the first article of this series, we defined what an HW arbiter is.
In this entry of the tutorial, we will see a simple implementation of a VHDL arbiter.

The arbiter of this example has three request inputs and three grant outputs. It has a fixed priority for the masters. The lower the master number, the higher its priority.
The block also has a busy signal. Arbitration of the bus is done only while it is inactive. If the bus has already been granted to an agent, even if a bigger priority master requests the bus, the current transaction must complete before the arbiter grants the bus to another master.

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VHDL arbiter

What is an arbiter?

An arbiter is a very common block used on HW designs.

I think I can find the best example of an arbiter at home. When my two kids were teenagers, I had only one car. On Friday and Saturday evenings, there was usually a conflict over who got to use the car. Usually, it was on me to decide (arbiter) who got the car. Not an easy task. (I still have only one car. It just happens that my kids are not teenagers anymore, and praise the Lord, they have their own cars).

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Introduction to signal processing – free book

Text adapted from the book website:

The book provides an applications-oriented introduction to digital signal processing written primarily for electrical engineering undergraduates. Practicing engineers and graduate students may also find it useful as a first text on the subject.

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Prototyping ARM Cortex-A using FPGA – Whitepaper

This whitepaper from ARM contains several techniques for prototyping ARM Cortex-A processors on FPGAs, including, among others:

How to cope with clock gating
Implementing RAMs
Design Partitioning
Handling Asynchronous resets

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Parallel Programming for FPGAs

Parallel Programming for FPGAs is an open-source book aimed at teaching hardware and software developers how to efficiently program FPGAs using high-level synthesis (HLS). The authors developed the book as we noticed a lack of material aimed at teaching people to effectively use HLS tools.
The book was developed over many years to serve as a primary reference for UCSD 237C — a hardware design class targeting first-year graduate students and advanced undergraduate students. We hope that you find it useful for learning more about HLS, FPGAs, and system-on-chip design.

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Are you ready for the Internet? (BBC archive 1994)

Magellan – a hardware monitor/debugger (II)

Part 2 – Registers monitoring

In this part we will integrate several blocks:

AXI infrastructure, defined on a Vivado block design, including a JTAG to AXI master
AXI-Lite registers block, with adaptations for this tutorial from the original one published on Code Snippets Seven segment driver for Basys 3 (presented in part 1 of this tutorial)
Seven segment decoder for Basys 3 (presented in part 1 of this tutorial)
An extension of the top block that was used in part 1, to instantiate the new blocks and add additional functionality.

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AXI-Lite register bank

This (relatively large) code snippet is about implementing a register bank with an AXI-Lite interface.

Some time ago I published a previous version of this module, based on an AXI-Lite code from Xilinx. From the feedback I received on Reddit, I understood that the Xilinx code for AXI-Lite slave, regretfully, is broken. So I wrote down my own version of the code and tested it thoroughly.

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