AMD-Xilinx extends series-7 product lifecycle

The 28nm AMD-Xilinx 7 series devices are used in industrial, automotive, test and measurement, aerospace and defense, and medical markets.

AMD-Xilinx has formally announced extended support for all 7 series FPGAs and adaptive SoCs through at least 2035, including the Spartan®-7 and Artix®-7 FPGAs, the entire Zynq®-7000 SoC portfolio, as well as Kintex®-7 and Virtex®-7 FPGAs. All speed and temperature grades are included.

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VHDL arbiters part IV – advanced simulation

Chapter 3 of this tutorial series on VHDL arbiters ended with the simulation of a round-robin arbiter. Here is the picture again, for reference:

Let’s take a look again at the marker placed at 670 ns. Two masters (1 and 2) are requesting the bus, but as we know, only one of them can receive it at a given moment, and in this case, it is master 2. But here happens something strange: Master 1 drops its request, even given the fact that it never received a grant signal! Although such behavior is possible, it is not common. The usual behavior of a master is to keep the request signal asserted until it receives a grant.

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Exploring Zynq MPSoc – free book

This book introduces the Zynq® MPSoC (Multi-Processor System-on-Chip), an embedded device from Xilinx® that combines a processing system that includes Arm® Cortex®-A53 application and Arm Cortex-R5 real-time processors, alongside FPGA programmable logic.

The book covers the architecture of the device, the design tools and methods, conventional hardware/software co-design approach, and the newer software-defined methodology, as well as hardware and software development, multiprocessing, safety, security and platform management, system booting, and  special features on PYNQ (a Python-based framework)  and machine learning applications.

This book should serve as a useful guide for those getting starting with, and the working with Zynq MPSoC, and equally as a reference for technical managers wishing to gain familiarity with the device and its associated design methodologies.

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VHDL arbiter – part III

This is the third part of a series of articles on VHDL arbiters.

In the first part, we talked about what a VHDL arbiter is.

In the second part, we saw the VHDL code for a fixed-priority VHDL arbiter.

When I talked about what a VHDL arbiter is, I gave the example of the single car we had at home, and how I had to decide who gets to use the car next Friday evening. In a typical situation, if both children ask for the car, the first thing they will account for is, who got the car the last time.

The fixed priority arbiter is the equivalent of always giving your car to the same child. It will, no doubts, create problems. If you don’t want to create problems, you will make a balanced assignment of the valued resource between the solicitors.

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Sphery vs. Shapes, a ray-traced game implemented on FPGA

As published on Reddit:

An open-source raytraced game runs as software or as just gates in an FPGA, achieving up to 50x efficiency gains.

The project was featured in the embedded news site CNX-Software today. An introductory video is at https://www.youtube.com/watch?v=hn3sr3VMJQU.

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Prototypical – FPGA prototyping free book

Making FPGA prototyping part of the design process early means actually thinking about how the design will be prototyped via an FPGA

In Prototypical – The Emergence of FPGA prototyping for SoC Design book, the authors tell the history of FPGA-based prototyping and three leading system providers – S2C, Cadence, and Synopsys.

First, the book describes how the need for co-verification evolved with chip complexity, where FPGAs got their start in verification, and why ASIC design benefits from prototyping technology.

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Intel announces new FPGA families

Image source: Intel PSG

Intel has announced these new/future FPGA families:

Intel® Agilex™ D-Series

For midrange FPGA applications like studio cameras, 8K video transport, and wireless infrastructure.

This new family incorporates an upgraded hard processor system (HPS), Enhanced DSP with AI Tensor Block, MIPI I/O support, and a hardened time-sensitive network controller (TSN). Intel Agilex D-Series devices also keep features from previous families like the 2nd-generation Intel® Hyperflex™ FPGA Architecture and high-speed SerDes transceivers.

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VHDL arbiter – part II

In the first article of this series, we defined what an HW arbiter is.
In this entry of the tutorial, we will see a simple implementation of a VHDL arbiter.

The arbiter of this example has three request inputs and three grant outputs. It has a fixed priority for the masters. The lower the master number, the higher its priority.
The block also has a busy signal. Arbitration of the bus is done only while it is inactive. If the bus has already been granted to an agent, even if a bigger priority master requests the bus, the current transaction must complete before the arbiter grants the bus to another master.

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VHDL arbiter

What is an arbiter?

An arbiter is a very common block used on HW designs.

I think I can find the best example of an arbiter at home. When my two kids were teenagers, I had only one car. On Friday and Saturday evenings, there was usually a conflict over who got to use the car. Usually, it was on me to decide (arbiter) who got the car. Not an easy task. (I still have only one car. It just happens that my kids are not teenagers anymore, and praise the Lord, they have their own cars).

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