Chapter 3 of this tutorial series on VHDL arbiters ended with the simulation of a round-robin arbiter. Here is the picture again, for reference:

Let’s take a look again at the marker placed at 670 ns. Two masters (1 and 2) are requesting the bus, but as we know, only one of them can receive it at a given moment, and in this case, it is master 2. But here happens something strange: Master 1 drops its request, even given the fact that it never received a grant signal! Although such behavior is possible, it is not common. The usual behavior of a master is to keep the request signal asserted until it receives a grant.

Continue reading “VHDL arbiters part IV – advanced simulation” →