Introduction to signal processing – free book

Text adapted from the book website:

The book provides an applications-oriented introduction to digital signal processing written primarily for electrical engineering undergraduates. Practicing engineers and graduate students may also find it useful as a first text on the subject.

Continue reading “Introduction to signal processing – free book” →

Parallel Programming for FPGAs

Parallel Programming for FPGAs is an open-source book aimed at teaching hardware and software developers how to efficiently program FPGAs using high-level synthesis (HLS). The authors developed the book as we noticed a lack of material aimed at teaching people to effectively use HLS tools.

The book was developed over many years to serve as a primary reference for UCSD 237C — a hardware design class targeting first-year graduate students and advanced undergraduate students. We hope that you find it useful for learning more about HLS, FPGAs, and system-on-chip design.

Continue reading “Parallel Programming for FPGAs” →

Magellan – a hardware monitor/debugger (II)

Part 2 – Registers monitoring

In this part we will integrate several blocks:

  1. AXI infrastructure, defined on a Vivado block design, including a JTAG to AXI master
  2. AXI-Lite registers block, with adaptations for this tutorial from the original one published on Code Snippets Seven segment driver for Basys 3 (presented in part 1 of this tutorial)
  3. Seven segment decoder for Basys 3 (presented in part 1 of this tutorial)
  4. An extension of the top block that was used in part 1, to instantiate the new blocks and add additional functionality.
Continue reading “Magellan – a hardware monitor/debugger (II)” →

AXI-Lite register bank

This (relatively large) code snippet is about implementing a register bank with an AXI-Lite interface.

Some time ago I published a previous version of this module, based on an AXI-Lite code from Xilinx. From the feedback I received on Reddit, I understood that the Xilinx code for AXI-Lite slave, regretfully, is broken. So I wrote down my own version of the code and tested it thoroughly.

Continue reading “AXI-Lite register bank” →

Finding Your Way Through Formal Verification – free book

Finding Your Way Through Formal Verification provides an introduction to formal verification methods. This book was written as a way to dip a toe in formal waters. You may be curious about formal verification, but you’re not yet sure it is right for your needs. Or you may need to plan and supervise formal verification activity as a part of a larger verification objective.

Continue reading “Finding Your Way Through Formal Verification – free book” →

Xilinx AXI stream tutorial – Part 2

Hi again,

In the previous chapter of this tutorial, we presented the AXI Streaming interface, its main signals, and some of its applications.

Now let’s go for the funnier stuff, that is, to actually make and test some VHDL code to implement our AXI master. We will proceed gradually, adding features as we go. At the end of this tutorial, you will have code that:

  • Implements an AXI master with variable packet length
  • Flow control support (ready and valid)
  • Option for generation of several kinds of data patterns
  • Testbench to check that all features work OK
  • Include an instantiation of Xilinx’s AXI Stream protocol checker IP to verify the correctness of our AXI master core.
Continue reading “Xilinx AXI stream tutorial – Part 2” →

Parallel to serial converter

This VHDL module receives parallel data as input at it outputs the data in serial format.

This VHDL module receives parallel data from the data_in bus when load is asserted. One clock after load is de-asserted, the data is serially transmitted out on the data_out line, MSB first, and valid is also asserted. The frame signal is asserted together with the end of the transmission (i.e. when the LSB is transmitted).

Continue reading “Parallel to serial converter” →