The 28nm AMD-Xilinx 7 series devices are used in industrial, automotive, test and measurement, aerospace and defense, and medical markets.
AMD-Xilinx has formally announced extended support for all 7 series FPGAs and adaptive SoCs through at least 2035, including the Spartan®-7 and Artix®-7 FPGAs, the entire Zynq®-7000 SoC portfolio, as well as Kintex®-7 and Virtex®-7 FPGAs. All speed and temperature grades are included.
Continue reading “AMD-Xilinx extends series-7 product lifecycle”Hi again,
In the previous chapter of this tutorial, we presented the AXI Streaming interface, its main signals, and some of its applications.
Now let’s go for the funnier stuff, that is, to actually make and test some VHDL code to implement our AXI master. We will proceed gradually, adding features as we go. At the end of this tutorial, you will have code that:
Hi,
In this series of articles, I am going to present the design of an AXI4-Stream master. As I often do in my tutorials, I will try to show the design procedure for the block, starting from a “bare bones” solution and gradually adding features to it.
Continue reading “Xilinx AXI Stream Tutorial”
SoC stands for System on Chip. Many electronic applications are based on microprocessors, memories, and peripherals. Traditionally the integration of these system components has been done at the board (PCB) level.
The never-stopping progression in electronic miniaturization has made it possible for many of these components (processor, memories, peripherals) to be integrated into a single package, thus called SoC.
Continue reading “SoC and MPSoC, what you wanted to know”
Basys 3 board with several PMOD boards attached – Credit: Digilent
The Basys 3 from Digilent is an FPGA Trainer Board based on AMD Xilinx’s Artix-7 FPGA.
In future blog entries, I will be including several projects based on this Trainer Board.
Continue reading “Basys 3 – An introduction”by Gilad Krupsky Reisman
The AXI Chip2Chip IP from Xilinx allows the designer to connect two or more FPGAs using an AXI bus implemented using transceivers running the Aurora64/66 protocol. While there is also an option to use regular FPGA pins if you don’t have transceivers, in my experience, it takes up too many pins to be relevant.
Continue reading “Xilinx AXI Chip2Chip for multi-FPGA design”
Image credit: Arty Z7 from Digilent
Are you going to make an FPGA design?
Are you asking yourself where to start, how to continue, and finish?
These are the basic steps of an FPGA design flow:
Continue reading “FPGA design flow summary”