For me, and for many other designers, the first time we saw the internal memory blocks in an FPGA came as a little shock.

Some of us were used to RAM devices used in Board Design. These devices use bidirectional data buses. Even the fastest memories, DDRn DRAMs, use bidirectional data buses (‘n’ has changed over the years, from plain DDR to current DDR4).

So, how come internal memories on an FPGA have TWO data buses? Isn’t that a waste of resources? Why don’t FPGAs have internal tri-state buses?

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