Tag: VHDL code

Pseudo random generator – Part II

Chapter 3 – Saving the output data

In the previous chapters of this tutorial, we saw how to make a simple LFSR module in VHDL and a testbench to verify its output results.

In this chapter, we will update our test bench to add data-saving capabilities. In this way we can:

  • Compare the VHDL data output with data generated by our reference design (in our case, a Python script algorithm)
  • Analyze the data output with other tools (again, in our case, we will use Python to produce an FFT analysis of the block output).

At the end of the chapter, you will be able to find a link to a GitHub repository with the complete files.

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Pseudo random generation Tutorial

In this tutorial, we will design a VHDL block. We will start with a very simple version of the block and gradually add features to it. We will also simulate it and test its outputs using a testbench and Python. During the process we will see:

  • How to start with a simple block and gradually add features and improvements
  • How to add a test bench (simulation)
  • Saving the block data output to files (from simulation)
  • Exporting files to Python in order to:
    • Verify the results, and
    • Analyze the results (in this case, using FFT)
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Coding and testing a Generic VHDL Downcounter

For synchronous logic, a timer and a counter are almost the same. After all, a timer counts clock units. That is why in many digital applications we see them called timers/counters.

The code below models a generic timer/counter, using unconstrained ports:

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Generic register with load

The VHDL code presented below models a synchronous parallel register with a load signal.

The register width is unconstrained (data_in and data_out don’t have a declared size). In previous versions of this code, I used generics to create a module with a configurable size. Using unconstrained ports instead of generics greatly improves the cleanliness and modularity of the code. The size of these signals will be known when the module is instantiated, in this case, by the test bench.

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