Chapter 3 – Saving the output data

In the previous chapters of this tutorial, we saw how to make a simple LFSR module in VHDL and a testbench to verify its output results.

In this chapter, we will update our test bench to add data-saving capabilities. In this way we can:

• Compare the VHDL data output with data generated by our reference design (in our case, a Python script algorithm)
• Analyze the data output with other tools (again, in our case, we will use Python to produce an FFT analysis of the block output).

At the end of the chapter, you will be able to find a link to a GitHub repository with the complete files.

Continue reading “Pseudo random generator – Part II” →