The VHDL code presented below models a binary to seven-segment decoder.
The decoder logic is a plain table, each ‘0’ in the output table corresponds to a segment lit on the seven-segment display.
Continue reading “Binary to seven-segment decoder”Month: August 2022
Coding and testing a Generic VHDL Downcounter
For synchronous logic, a timer and a counter are almost the same. After all, a timer counts clock units. That is why in many digital applications we see them called timers/counters.
The code below models a generic timer/counter, using unconstrained ports:
Continue reading “Coding and testing a Generic VHDL Downcounter”A Fresh Look at HLS Value
by Bernard Murphy
I’ve written several articles on High-Level Synthesis (HLS), designing in C, C++, or SystemC, then synthesizing to RTL. There is an unquestionable appeal to the concept. A higher level of abstraction enables a function to be described in fewer lines of code (LOC). This immediately offers higher productivity and implies fewer bugs because the number of bugs in any kind of code scales pretty reliably with LOC. Simulation for architectural design and validation runs multiple orders of magnitude faster, allowing for broader experimentation with options. It also can run much larger tests like image recognition on streaming video, a tough goal for RTL simulations. Yet these methods have largely been restricted to specialized design objectives it seemed. Signal processing functions, some simple ML inference engines, that sort of thing.
To read the rest of the article, please go to SemiWiki
Generic demultiplexer and decoder
The demultiplexer receives one data bit din as input and routes it to one of ‘n’ possible outputs. The output is selected according to the value of the sel input.
The demultiplexer size is configurable via a generic parameter SEL_W.
The decoder is a simpler version of a demultiplexer, it will be shown after the code for the demultiplexer and the Vivado simulation results below:
Continue reading “Generic demultiplexer and decoder”Generic register with load
The VHDL code presented below models a synchronous parallel register with a load signal.
The register width is unconstrained (data_in and data_out don’t have a declared size). In previous versions of this code, I used generics to create a module with a configurable size. Using unconstrained ports instead of generics greatly improves the cleanliness and modularity of the code. The size of these signals will be known when the module is instantiated, in this case, by the test bench.
Continue reading “Generic register with load”