Generic demultiplexer and decoder

The demultiplexer receives one data bit din as input and routes it to one of ‘n’ possible outputs. The output is selected according to the value of the sel input.

The demultiplexer size is configurable via a generic parameter SEL_W.

The decoder is a simpler version of a demultiplexer, it will be shown after the code for the demultiplexer and the Vivado simulation results below:

library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;

entity demux is 
	generic ( SEL_W		: natural := 4 );	
	
	port (
		-- inputs
		din: 		in std_logic;
		sel:		in std_logic_vector (SEL_W-1 downto 0);
		
		-- outputs
		data_out: 	out std_logic_vector (2**SEL_W-1 downto 0)
	);
end demux;

architecture rtl of demux is

begin 

	demux_pr: process(sel, din)
	begin
		-- set all the outputs to '0' to avoid inferred latches
		data_out <= (others => '0');
		-- Set input in correct line
		data_out(to_integer(unsigned(sel))) <= din;
	end process;

end rtl;

On the simulation waveform below, at time = 50 ns (first marker), the sel input cycles from ‘0’ to ‘7’, and since din is constantly high, the corresponding outputs from data_out[0] to data_out[7] are asserted. At t=240 ns (second marker), the sel input is set to ‘3’ and we can see that data_out[3] follows the din input. You are invited to analyze by yourself what happens at the third marker.

The source code and testbench for the demultiplexer can be found on GitHub

The decoder is simpler than the demultiplexer, there isn’t a din input. The sel input (of width SEL_W) is decoded into one output active (there are 2^SEL_W outputs). A demultiplexer can behave as a decoder if its data input is at a constant value of ‘1’.

library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;

entity decoder is 
	generic ( SEL_W		: natural := 4 );	
	
	port (	
		-- inputs
		sel:		in std_logic_vector (SEL_W-1 downto 0);
		
		-- outputs
		data_out: 	out std_logic_vector (2**SEL_W-1 downto 0)
	);
end decoder;

architecture rtl of decoder is

begin 
	demux_pr: process(sel)
	begin
		-- set all the outputs to '0' to avoid inferred latches
		data_out <= (others => '0');
		-- Set input in correct line
		data_out(to_integer(unsigned(sel))) <= '1';
	end process;

end rtl;

The source code for the decoder can be found on GitHub