The demultiplexer receives one data bit din as input and routes it to one of ‘n’ possible outputs. The output is selected according to the value of the sel input.
The demultiplexer size is configurable via a generic parameter SEL_W.
The decoder is a simpler version of a demultiplexer, it will be shown after the code for the demultiplexer and the Vivado simulation results below:
Continue reading “Generic demultiplexer and decoder”The VHDL code presented below models a synchronous parallel register with a load signal.
The register width is unconstrained (data_in and data_out don’t have a declared size). In previous versions of this code, I used generics to create a module with a configurable size. Using unconstrained ports instead of generics greatly improves the cleanliness and modularity of the code. The size of these signals will be known when the module is instantiated, in this case, by the test bench.
Continue reading “Generic register with load”