In this tutorial, we will design a VHDL block. We will start with a very simple version of the block and gradually add features to it. We will also simulate it and test its outputs using a testbench and Python. During the process we will see:
- How to start with a simple block and gradually add features and improvements
- How to add a test bench (simulation)
- Saving the block data output to files (from simulation)
- Exporting files to Python in order to:
- Verify the results, and
- Analyze the results (in this case, using FFT)