Finding Your Way Through Formal Verification – free book

Finding Your Way Through Formal Verification provides an introduction to formal verification methods. This book was written as a way to dip a toe in formal waters. You may be curious about formal verification, but you’re not yet sure it is right for your needs. Or you may need to plan and supervise formal verification activity as a part of a larger verification objective.

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Xilinx AXI stream tutorial – Part 2

Hi again,

In the previous chapter of this tutorial, we presented the AXI Streaming interface, its main signals, and some of its applications.

Now let’s go for the funnier stuff, that is, to actually make and test some VHDL code to implement our AXI master. We will proceed gradually, adding features as we go. At the end of this tutorial, you will have code that:

  • Implements an AXI master with variable packet length
  • Flow control support (ready and valid)
  • Option for generation of several kinds of data patterns
  • Testbench to check that all features work OK
  • Include an instantiation of Xilinx’s AXI Stream protocol checker IP to verify the correctness of our AXI master core.
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Parallel to serial converter

This VHDL module receives parallel data as input at it outputs the data in serial format.

This VHDL module receives parallel data from the data_in bus when load is asserted. One clock after load is de-asserted, the data is serially transmitted out on the data_out line, MSB first, and valid is also asserted. The frame signal is asserted together with the end of the transmission (i.e. when the LSB is transmitted).

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SoC and MPSoC, what you wanted to know

Image credit: Xilinx

SoC stands for System on Chip. Many electronic applications are based on microprocessors, memories, and peripherals. Traditionally the integration of these system components has been done at the board (PCB) level.

The never-stopping progression in electronic miniaturization has made it possible for many of these components (processor, memories, peripherals) to be integrated into a single package, thus called SoC.

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Magellan – a hardware monitor/debugger

Part 1 – Seven segment display

The Basys 3 board has a plethora of interactive resources: push buttons, switches, LEDs, and a four-digit seven-segment display, among others.

In this series of articles, we will describe Magellan. Magellan is a hardware monitor/debugger which we will put to use for debugging our designs.

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FreeRange – Logic/Verilog free books & courses

Free Range’s author James Mealy has a long trajectory in the free diffusion of logic design.

On this site, you can find free books (Logic foundation and Verilog), selected chapters of the course on video, and solutions to the course’s lab exercises.

From the author page :

I started collecting digital design textbooks after arriving at Cal Poly; I was sure that writing books meant having all the books possible on the subject and arranging the information differently. What I found was that I simply didn’t like the approach taken in every digital design textbook I’ve ever read. This led me to take a different approach, which I’ve done in the FreeRange series of courseware. I put more comments regarding the approach on a different page and in the actual textbooks as well.

Free Range – Digital Design and Verilog Modeling

You may also want to check: Free Range VHDL (free book)